The present invention relates generally to digital electronic circuits and more particularly to the digital drivers used to generate the logic signals used by those circuits.
Typically, modern digital circuits include devices from many different digital logic families, such as transistor-transistor logic (TTL), metal-oxide semiconductor (MOS) and complimentary metal-oxide semiconductor (CMOS). It is often desirable to combine different families within a single system, or even a single chip. A problem exist, however, in that each family has unique characteristics and requirements, such as supply voltages and output levels, and using a high voltage device output level to drive a low voltage device could damage the low voltage device.
Many systems deal with this problem by using a mixed power supply having for example a 5 V terminal and 2.5 V terminal. FIG. 1 shows a typical prior art CMOS driver 100, using a mixed power supply (Vcc1, Vcc2), to generate an output at the lower (Vcc2) voltage level. Driver 100 includes an input terminal 102, a first PMOS transistor 104, a first NMOS transistor 106, a second PMOS transistor 108, a second NMOS transistor 110, a conductor 112, a first voltage supply terminal 114, a second voltage supply terminal 116, a ground terminal 118, and an output terminal 120.
First PMOS transistor 104 has a source terminal 122 connected to first voltage supply terminal 114, a drain terminal 124 connected to conductor 112, and a gate terminal 126 connected to input terminal 102. First NMOS transistor 106 has a drain terminal 128 connected to conductor 112, a source terminal 130 connected to ground terminal 118, and a gate terminal connected to input terminal 102. Second PMOS transistor 108 has a source terminal 134 connected to second voltage supply terminal 116, a drain terminal 136 connected to output terminal 120, and a gate terminal 138 connected to conductor 112. Second NMOS transistor 110 has a drain terminal 140 connected to output terminal 120, a source terminal 142 connected to ground terminal 118, and a gate terminal 144 connected to conductor 102.
When the voltage at input terminal 102 is low, first PMOS transistor 104 is "on," so that its drain terminal 124 and conductor 112 are pulled up near Vcc1, the voltage on first voltage supply terminal 114. The low voltage on input terminal 102 also turns first NMOS transistor 106 "off," so that no current flows from conductor 112 through transistor 106 to ground. Since the voltage on conductor 112 is near Vcc1, second NMOS transistor 110 is "on" and pulls its drain 140 and output terminal 120 near ground. The high voltage on conductor 112 also turns second PMOS transistor 108 "off," so that no current flows from second voltage supply terminal 116 to output terminal 120. Thus, responsive to a logical low voltage on input terminal 102, driver 100 produces a logical low voltage on output terminal 120.
When input terminal 102 is brought to a high voltage, however, first NMOS transistor 106 is turned "on" so that its drain terminal 128 and conductor 112 are pulled near ground. The high signal on input terminal 102 also turns first PMOS transistor 104 "off" so that no current flows from first supply voltage terminal 114 through transistor 104 to conductor 112. The low voltage on conductor 112 turns second PMOS transistor 108 "on," pulling its drain terminal 136 near Vcc2, and turns second NMOS transistor 110 "off" so that no current can flow from output terminal 120 through transistor 110 to ground terminal 118. Thus, responsive to a logical high voltage on input terminal 102, driver 100 produces a logical high voltage, very close to Vcc2, on output terminal 120.
Using a mixed power supply is not, however, a total solution. First, it is undesirable to increase the number of supply pins that must be provided on an integrated circuit chip. Further, it would be impractical to provide a separate supply terminal for every possible voltage level.
Intermediate voltages can sometimes be produced using diodes, but often the desired voltage level is not an integral number of diode voltage drops from a supply level. For example, if an output voltage of 4.0 V is required, and the power supply has a 5.0 V pin, one diode drop would produce a (5 V-0.6 V=) 4.4 V output and two diode drops would produce a 3.8V output, neither achieving the desired 4.0V.
Generally, the amount of static current required for the on-chip production of output voltages is roughly equivalent to the amount of static current required at the output. This amount of static current is usually unacceptable from the standpoint of power dissipation. Further, it is desirable that the static current required to produce each output voltage be much smaller than the output current requirements. Therefore, what is needed is a driver that generates, on-chip, the intermediate voltages used to drive the outputs, and whose static current requirements are far less than its output current requirements.